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TCL 40-E371C4-PWA1XG 

TROUBLESHOOTING 

1. Fuse blowing

Check Diode D1 > D4 for any short

Check the IGBT K12A50D For any short.

Replace FAN7930 Pwm driver

2. Power supply doesn’t starts

Check the resistors R307,R308,R309,R310 , is any of them is open or not . This resistor network provides the staring supply to FAN7930.

Replace FAN7930 , FSFR1700XS

Check the diode at the secondary side or the SMPS for any short. 

FSFR1700XS

The FSFR-XS series includes highly integrated power switches designed for high-efficiency half-bridge resonant converters. Offering everything necessary to build a reliable and robust resonant converter, the FSFR- XS series simplifies designs while improving productivity and performance. The FSFR-XS series combines power MOSFETs with fast-recovery type body diodes, a high- side gate-drive circuit, an accurate current controlled oscillator, frequency limit circuit, soft-start, and built-in protection functions. The high-side gate-drive circuit has common-mode noise cancellation capability, which guarantees stable operation with excellent noise immunity. The fast-recovery body diode of the MOSFETs improves reliability against abnormal operation conditions, while minimizing the effect of reverse recovery. Using the zero-voltage-switching (ZVS) technique dramatically reduces the switching losses and significantly improves efficiency. The ZVS also reduces the switching noise noticeably, which allows a small- sized Electromagnetic Interference (EMI) filter. The FSFR-XS series can be applied to resonant converter topologies such as series resonant, parallel resonant, and LLC resonant converters.

PIN CONFIGURATION OF FSFR1700XS

1 VDL - This is the drain of the high-side MOSFET, typically connected to the input DC link voltage

2 AR - This pin is for discharging the external soft-start capacitor when any protections are triggered. When the voltage of this pin drops to 0.2 V, all protections are reset and the controller starts to operate again.

3 RT- This pin programs the switching frequency. Typically, an opto-coupler is connected to cont the switching frequency for the output voltage regulation.

4 CS - This pin senses the current flowing through the low-side MOSFET. Typically, negative voltage is applied on this pin.

5 SG - This pin is the control ground.

6 PG - This pin is the power ground. This pin is connected to the source of the low-side MOSFET.

7 LVCC - This pin is the supply voltage of the control IC.

8 NC - No connection.

9 HVCC - This is the supply voltage of the high-side gate-drive circuit IC.

10 VCTR - This is the drain of the low-side MOSFET. Typically, a transformer is connected to this pin.

FAN7930

The FAN7930 is an active power factor correction (PFC) controller for boost PFC applications that operate in critical conduction mode (CRM). It uses a voltage-mode PWM that compares an internal ramp signal with the error amplifier output to generate a MOSFET turn-off signal. Because the voltage-mode CRM PFC controller does not need rectified AC line voltage information, it saves the power loss of an input voltage sensing network necessary for a current-mode CRM PFC controller. FAN793O provides over-voltage protection, open- feedback protection, over-current protection, input- voltage-absent detection, and under-voltage lockout protection. The PFC-ready pin can be used to trigger other power stages when PFC output voltage reaches the proper level with hysteresis. The FAN7930 can be disabled if the INV pin voltage is lower than O.45\/ and the operating current decreases to a very low level. Using a new variable on-time control method, THD is lower than the conventional CRM boost PFC ICs.

PIN CONFIGURATION OF FAN7930

1 INV

This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter should be resistively divided to 2.5V.

2 RDY

This pin is used to detect PFC output voltage reaching a pre-determined value. When output voltage reaches 89% of rated output voltage, this pin is pulled HIGH, which is an (open drain) output type.

3 COMP

This pin is the output of the transconductance error amplifier. Components for the output voltage compensation should be connected between this pin and GND.

4 CS

This pin is the input of the over-current protection comparator. The MOSFET current is sensed using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is included to filter switching noise.

5 ZCD

This pin is the input of the zero-current detection block. If the voltage of this pin goes higher than 1.5V, then goes lower than 1.4V, the MOSFET is turned on.

6 GND

This pin is used for the ground potential of all the pins. For proper operation, the signal ground and the power ground should be separated.

7 OUT

This pin is the gate drive output. The peak sourcing and sinking current levels are +500mA and - 800mA, respectively. For proper operation, the stray inductance in the gate driving path must be minimized.

8 Vcc

This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.

POWER SUPPLY SCHEMATIC DIAGRAM 

PFC SECTION 

SMPS SECTION 

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Category: LED Television Repair and service 

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Samsung UE32D4000

Troublshooting 

Fuse blowing:

If the fuse is blowing of continuously then check the flowing components 

MOV VX801s – If it’s found short then replace it 

Bridge rectifier BD810 – Check is any one of the diode is short or not 

Check the IGBT TF12N65 For any short if found short replace it  

Replace ICM801 FAN 7602

ABOUT FAN7602 PWM Controller

The FAN7602 is a green current mode PWM controller. It is specially designed for off-line adapter application, DVDP, VCR, LCD monitor application, and auxiliary power supplies. The internal high-voltage start-up switch and the burstmode operation reduce the power loss in standby mode. Because of the internal start-up switch and the burst mode, it is possible to supply 0.5W load, limiting the input power to under 1W when the input line voltage is 265V AC. On no-load condition, the input power is under 0.3W. The maximum power can be limited constantly, regardless of the line voltage change, using the power limit function. The switching frequency is internally fixed at 65kHz and the frequency modulation technique reduces EMI. The FAN7602 includes various protections for the system reliability and the internal soft-start prevents the output voltage overshoot at start-up.

1 LUVP  - Line Under-Voltage Protection Pin. This pin is used to protect the set when the input voltage is lower than the rated input voltage range.

2 Latch/Plimit  - Latch Protection and Power Limit Pin. When the pin voltage exceeds 4V, the latch protection works. The latch protection is reset when the VCC voltage is lower than 5V. For the power limit function, the Over-Current Protection (OCP) level decreases as the pin voltage increases.

3 CS/FB - Current Sense and Feedback Pin. This pin is used to sense the MOSFET current

for the current mode PWM and OCP. The output voltage feedback information and

the current sense information are added using an external RC filter.

4 GND - Ground Pin. This pin is used for the ground potential of all the pins. For proper oper ation, the signal ground and the power ground should be separated.

5 OUT - Gate Drive Output Pin. This pin is an output pin to drive an external MOSFET. The peak sourcing current is 450mA and the peak sinking current is 600mA. For proper operation, the stray inductance in the gate driving path must be minimized.

6 V CC Supply - Voltage Pin. IC operating current and MOSFET driving current are supplied using this pin.

7 NC - No Connection.

8 Vstr  - Start-up Pin. This pin is used to supply IC operating current during IC start-up. After start-up, the internal JFET is turned off to reduce power loss.

SMPS NOTES

D.C. to DC convertor and DC to AC converter belong to the category of switched mode power supply (SMPS). The various types of voltage regulator used in linear power supplies (LPS), fall in the category of dissipative regulator, as they have a voltage control element usually transistor or zener diode which dissipates power equal to the voltage difference between an unregulated input voltage and a fixed supply voltage multiplied by the current flowing through it. The switching regulator acts as a continuously variable power converter and hence its efficiency is negligibly affected by the voltage difference. hence the switching regulator is also known as “non-dissipative regulator” in a SMPS, The input DC supply is chopped at a higher frequency around 15 to 50KHz using an active device like the BJT power MOSFET or SCR and the convertor transformer There are three basic switch regulators 1.Step down or buck switching regulators. 2.Step up or boost switching regulator. 3.Inverting type switching regulator

COMMON LED DRIVE WORKING

There are large arrays of LEDs located behind the LCD panel in a typical LCD TV LED. In this array are a large number of parallel channels of LEDs connected in series depending on the size of the TV and the type of backlighting, for example edge backlighting (less LEDs but more in series) or direct backlighting (more LEDs in parallel) . The LED voltage (VLED) is provided by the White LED Backlight Driver Board to each LED channel and is regulated to a level needed by the highest voltage required to maximize the light output of each LED string . Depending upon the power supply requirements determined by the number of LEDs in the string or grouping of parallel LED strings, the up-stream power source for the LED backlight driver board may be a DC/DC step-up boost converter, a DC/DC step-down converter or more commonly an AC/DC converter . In the case where supply voltage is lower than the required VLED, a step-up boost converter will be used . As an example, a LED boost converter LED backlighting system will be described in detail in this paper for a direct backlighting application, however the theory of operation will also apply to both the step-down converter and AC/DC converter situation .

High brightness LEDs used in LCD backlighting require high LED current which also equates to higher LED forward voltage . For example, if a user wants to set the LED current to 80mA maximum, a minimum of 3 .65V forward voltage must be provided to each LED in the string . If the power supply can only provide 3 .6V to each LED, then the maximum LED current is limited to 74mA .

POWER SUPPLY SCHEMATICS 

LED DRIVER SCHEMATIC 

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SAMSUNG BN44-00191A

FSQ0165

Description

A Valley Switching Converter generally shows lower EMI and higher power conversion efficiency than a conventional hard-switched converter with a fixed switching frequency. The FSQ-series is an integrated Pulse-Width Modulation (PWM) controller and SenseFET specifically designed for valley switching operation with minimal external components. The PWM controller includes an integrated fixed-frequency oscillator, under-voltage lockout, Leading-Edge Blanking (LEB), optimized gate driver, internal soft-start, temperature-compensated precise current sources for loop compensation, and self-protection circuitry. Compared with discrete MOSFET and PWM controller solutions, the FSQ-series reduces total cost, component count, size and weight; while simultaneously increasing efficiency, productivity, and system reliability. This device provides a basic platform for cost-effective designs of valley switching fly-back converters.

PIN CONFIGURATION

1 GND

SenseFET source terminal on primary side and internal control ground.

2 Vcc

Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied from pin 5 (Vstr) via an internal switch during startup. It is not until \/CC reaches the UVLO upper threshold (12V) that the internal startup switch opens and device power is supplied via the auxiliary transformer winding.

3 Vfb

The feedback voltage pin is the non-inverting input to the PWM comparator. It has a 0.9mA current source connected internally while a capacitor and opto-coupler are typically connected externally. There is a time delay while charging external capacitor C“, from 3V to 6V using an internal 5pA current source. This delay prevents false triggering under transient conditions, but still allows the protection mechanism to operate under true overload conditions.

4 Sync

This pin is internally connected to the sync-detect comparator for valley switching. Typically the voltage of the auxiliary winding is used as Sync input voltage and external resistors and capacitor are needed to make delay to match valley point. The threshold of the internal sync comparator is 0.?Vf0.2V.

5 Vstr

This pin is connected to the rectified AC line voltage source. At startu p, the internal switch supplies internal bias and charges an external storage capacitor placed between the Vcc pin and ground. Once the \/CC reaches 12V, the internal switch is opened.

6,7,8 Drain

The drain pins are designed to connect directly to the primary lead of the transformer and are capable of switching a maximum of 650V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance.

FAN7530

Description

The FAN7530 is an active power factor correction (PFC) controller for the boost PFC applications that operates in critical conduction mode (CRM). It uses the voltage mode PWM that compares an internal ramp signal with the error amplifier output to generate MOSFET turn-off signal. Because the voltage mode CRM PFC controller does not need the rectified AC line voltage information, it can save the power loss of the input voltage sensing net- work necessary for the current mode CRM PFC control- ler. FAN753O provides many protection functions such as over voltage protection, open-feedback protection, over- current protection, and under-voltage lockout protection. The FAN7530 can be disabled if the INV pin voltage is lower than 0.45V and the operating current decreases to 65uA. Using a new variable on-time control method, THD is lowerthan the conventional CRM boost PFC lCs.

PIN COFIGURATION

1 INV

This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter should be resistively divided to 2.5V.

2 MOT

This pin is used to set the slope of the internal ramp. The voltage of this pin is maintained at 3V. If a resistor is connected between this pin and GND, current flows out of the pin and the slope of the internal ramp is proportional to this current.

3 COMP

This pin is the output of the transconductance error amplifier. Components for the out- put voltage compensation should be connected between this pin and GND.

4 CS

This pin is the input of the over-current protection comparator. The MOSFET current is sensed using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is included to filter switching noise.

5 ZCD

This pin is the input of the zero current detection block. If the voltage of this pin goes higherthan 1.5V, then goes lowerthan 1.4V, the MOSFET is turned on.

6 GND

This pin is used for the ground potential of all the pins. For proper operation, the signal ground and the power ground should be separated.

7 OUT

This pin is the gate drive output. The peak sourcing and sinking current levels are +500mA and -800mA respectively. For proper operation, the stray inductance in the gate driving path must be minimized.

8 Vcc

This pin is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.

POWER SUPPLY SCHEMATIC DIAGRAM 

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Category: LCD Power Supply Repair and Service 

Contents of this article 

LOEWE Spheres R 32 HD

MC33262 Power Factor Controllers

Description
The MC34262/MC33262 are active power factor controllers specifically designed for use as a preconverter in electronic ballast and in off–line power converter applications. These integrated circuits feature an internal startup timer for stand–alone applications, a one quadrant multiplier for near unity power factor, zero current detector to ensure critical conduction operation, transconductance error amplifier, quickstart circuit for enhanced startup, trimmed internal bandgap reference, current sensing comparator, and a totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of an overvoltage comparator to eliminate runaway output voltage due to load removal, input under voltage lockout with hysteresis, cycle–by–cycle current limiting, multiplier output clamp that limits maximum peak switch current, an RS latch for single pulse metering, and a drive output high state clamp for MOSFET gate protection. These devices are available in dual–in–line and surface mount plastic packages.

FEATURES 

Overvoltage Comparator Eliminates Runaway Output Voltage

Internal Startup Timer

One Quadrant Multiplier

Zero Current Detector

Trimmed 2% Internal Bandgap Reference

Totem Pole Output with High State Clamp

Undervoltage Lockout with 6.0 V of Hysteresis

Low Startup and Operating Current

Supersedes Functionality of SG3561 and TDA4817

L6599

Description
The L6599 is a double-ended controller specific for the resonant half-bridge topology. It provides 50 % complementary duty cycle: the high-side switch and the low-side switch are driven ON\OFF 180° out-of-phase for exactly the same time. Output voltage regulation is obtained by modulating the operating frequency. A fixed deadtime inserted between the turn-OFF of one switch and the turn-ON of the other one guarantees soft-switching and enables high-frequency operation.
To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage floating structure able to withstand more than 600 V with a synchronous-driven high-voltage DMOS that replaces the external fast-recovery bootstrap diode. The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator.
At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non linear to minimize output voltage overshoots; its duration is programmable as well. The IC can be forced to enter a controlled burst-mode operation at light load, so as to keep converter's input consumption to a minimum. IC's functions include a not-latched active-low disable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for OCP with frequency shift and delayed shutdown with automatic restart. A higher level OCP latches off the IC if the first-level protection is not sufficient to control the primary current. Their combination offers complete protection against overload and short circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or OVP.
An interface with the PFC controller is provided that enables to switch off the pre-regulator during fault conditions, such as OCP shutdown and DIS high, or during burst-mode operation.

PIN CONFIGURATION 
1 C SS
Soft start. This pin connects an external capacitor to GND and a resistor to RFmin (pin 4) that set both the maximum oscillator frequency and the time constant for the frequency shift that occurs as the chip starts up (soft-start). An internal switch discharges this capacitor every time the chip turns OFF (VCC < UVLO, LINE < 1.25 V or > 6 V, DIS > 1.85 V, ISEN > 1.5 V, DELAY > 3.5 V) to make sure it will be soft-started next, and when the voltage on the current sense pin (ISEN) exceeds 0.8V, as long as it stays above 0.75 V.
2 DELAY
Delayed shutdown upon overcurrent. A capacitor and a resistor are connected from this pin to GND to set both the maximum duration of an overcurrent condition before the IC stops switching and the delay after which the IC restarts switching. Every time the voltage on the ISEN pin exceeds 0.8 V the capacitor is charged by an internal 150µA current generator and is slowly discharged by the external resistor. If the voltage on the pin reaches 2 V, the soft start capacitor is completely discharged so that the switching frequency is pushed to its maximum value and the 150 µA is kept always on. As the voltage on the pin exceeds 3.5 V the IC stops switching and the internal generator is turned OFF, so that the voltage on the pin will decay because of the external resistor. The IC will be soft-restarted as the voltage drops below 0.3V. In this way, under short circuit conditions, the converter will work intermittently with very low input average power.
3 CF
Timing capacitor. A capacitor connected from this pin to GND is charged and discharged by internal current generators programmed by the external network connected to pin 4 (RFmin) and determines the switching frequency of the converter.

4 RFmin
Minimum oscillator frequency setting. This pin provides a precise 2 V reference and a resistor connected from this pin to GND defines a current that is used to set the minimum oscillator frequency. To close the feedback loop that regulates the converter output voltage by modulating the oscillator frequency, the phototransistor of an optocoupler will be connected to this pin through a resistor. The value of this resistor will set the maximum operating frequency. An R-C series connected from this pin to GND sets frequency shift at start-up to prevent excessive energy inrush (soft-start).
5 STBY
Burst-mode operation threshold. The pin senses some voltage related to the feedback control, which is compared to an internal reference (1.25 V). If the voltage on the pin is lower than the reference, the IC enters an idle state and its quiescent current is reduced. The chip restarts switching as the voltage exceeds the reference by 50 mV. Soft-start is not invoked. This function realizes burst-mode operation when the load falls below a level that can be programmed by properly choosing the resistor connecting the optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if burst-mode is not used.
6 ISEN
Current sense input. The pin senses the primary current though a sense resistor or a capacitive divider for lossless sensing. This input is not intended for a cycle-by-cycle control; hence the voltage signal must be filtered to get average current information. As the voltage exceeds a 0.8 V threshold (with 50 mV hysteresis), the soft-start capacitor connected to pin 1 is internally discharged: the frequency increases hence limiting the power throughput. Under output short circuit, this normally results in a nearly constant peak primary current. This condition is allowed for a maximum time set at pin 2. If the current keeps on building up despite this frequency increase, a second comparator referenced at 1.5 V latches the device off and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.
7 LINE
Line sensing input. The pin is to be connected to the high-voltage input bus with a resistor divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage below 1.25 V shuts down (not latched) the IC, lowers its consumption and discharges the soft-start capacitor. IC’s operation is re-enabled (soft-started) as the voltage exceeds 1.25 V. The comparator is provided with current hysteresis: an internal 15 µA current generator is ON as long as the voltage applied at the pin is below 1.25 V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on the pin is top-limited by an internal zener. Activating the zener causes the IC to shut down (not latched). Bias the pin between 1.25 and 6 V if the function is not used.
8 DIS
Latched device shutdown. Internally the pin connects a comparator that, when the voltage on the pin exceeds 1.85 V, shuts the IC down and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the VCC pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.
9 PFC_STOP
Open-drain ON/OFF control of PFC controller. This pin, normally open, is intended for stopping the PFC controller, for protection purpose or during burst-mode operation. It goes low when the IC is shut down by DIS > 1.85 V, ISEN > 1.5 V, LINE > 6 V and STBY < 1.25 V. The pin is pulled low also when the voltage on pin DELAY exceeds 2V and goes back open as the voltage falls below 0.3V. During UVLO, it is open. Leave the pin unconnected if not used.
10 GND
Chip ground. Current return for both the low-side gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return.

11 LVG
Low-side gate-drive output. The driver is capable of 0.3 A min. source and 0.8 A min. sink peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively pulled to GND during UVLO.
12 VCC
Supply Voltage of both the signal part of the IC and the low-side gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC.
13 N.C.

High-voltage spacer. The pin is not internally connected to isolate the high-voltage pin and ease compliance with safety regulations (creepage distance) on the PCB.

14 OUT

High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground.
15 HVG
High-side floating gate-drive output. The driver is capable of 0.3 A min. source and 0.8A min. sink peak current to drive the upper MOSFET of the half-bridge leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not floating during UVLO.
16 VBOOT
High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase with the low-side gate-drive. This patented structure replaces the normally used external diode.

 POWER SUPPLY SCHEMATIC DIGRAM 

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Category: LCD Television Repair and Service 

Contents of this article

• Power supply circuit digram 
• L6599 Details 
• SG6961 Details  

PHILIPS 32HFL5382 - 37HFL5382 - 42HFL5382

Description
The L6599 is a double-ended controller specific for the resonant half-bridge topology. It provides 50 % complementary duty cycle: the high-side switch and the low-side switch are driven ON\OFF 180° out-of-phase for exactly the same time. Output voltage regulation is obtained by modulating the operating frequency. A fixed deadtime inserted between the turn-OFF of one switch and the turn-ON of the other one guarantees soft-switching and enables high-frequency operation.
To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage floating structure able to withstand more than 600 V with a synchronous-driven high-voltage DMOS that replaces the external fast-recovery bootstrap diode. The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable oscillator.
At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. This frequency shift is non linear to minimize output voltage overshoots; its duration is programmable as well. The IC can be forced to enter a controlled burst-mode operation at light load, so as to keep converter's input consumption to a minimum. IC's functions include a not-latched active-low disable input with current hysteresis useful for power sequencing or for brownout protection, a current sense input for OCP with frequency shift and delayed shutdown with automatic restart. A higher level OCP latches off the IC if the first-level protection is not sufficient to control the primary current. Their combination offers complete protection against overload and short circuits. An additional latched disable input (DIS) allows easy implementation of OTP and/or OVP.
An interface with the PFC controller is provided that enables to switch off the pre-regulator during fault conditions, such as OCP shutdown and DIS high, or during burst-mode operation.

PIN CONFIGURATION 
1 C SS
Soft start. This pin connects an external capacitor to GND and a resistor to RFmin (pin 4) that set both the maximum oscillator frequency and the time constant for the frequency shift that occurs as the chip starts up (soft-start). An internal switch discharges this capacitor every time the chip turns OFF (VCC < UVLO, LINE < 1.25 V or > 6 V, DIS > 1.85 V, ISEN > 1.5 V, DELAY > 3.5 V) to make sure it will be soft-started next, and when the voltage on the current sense pin (ISEN) exceeds 0.8V, as long as it stays above 0.75 V.
2 DELAY
Delayed shutdown upon overcurrent. A capacitor and a resistor are connected from this pin to GND to set both the maximum duration of an overcurrent condition before the IC stops switching and the delay after which the IC restarts switching. Every time the voltage on the ISEN pin exceeds 0.8 V the capacitor is charged by an internal 150µA current generator and is slowly discharged by the external resistor. If the voltage on the pin reaches 2 V, the soft start capacitor is completely discharged so that the switching frequency is pushed to its maximum value and the 150 µA is kept always on. As the voltage on the pin exceeds 3.5 V the IC stops switching and the internal generator is turned OFF, so that the voltage on the pin will decay because of the external resistor. The IC will be soft-restarted as the voltage drops below 0.3V. In this way, under short circuit conditions, the converter will work intermittently with very low input average power.
3 CF
Timing capacitor. A capacitor connected from this pin to GND is charged and discharged by internal current generators programmed by the external network connected to pin 4 (RFmin) and determines the switching frequency of the converter.

4 RFmin
Minimum oscillator frequency setting. This pin provides a precise 2 V reference and a resistor connected from this pin to GND defines a current that is used to set the minimum oscillator frequency. To close the feedback loop that regulates the converter output voltage by modulating the oscillator frequency, the phototransistor of an optocoupler will be connected to this pin through a resistor. The value of this resistor will set the maximum operating frequency. An R-C series connected from this pin to GND sets frequency shift at start-up to prevent excessive energy inrush (soft-start).
5 STBY
Burst-mode operation threshold. The pin senses some voltage related to the feedback control, which is compared to an internal reference (1.25 V). If the voltage on the pin is lower than the reference, the IC enters an idle state and its quiescent current is reduced. The chip restarts switching as the voltage exceeds the reference by 50 mV. Soft-start is not invoked. This function realizes burst-mode operation when the load falls below a level that can be programmed by properly choosing the resistor connecting the optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if burst-mode is not used.
6 ISEN
Current sense input. The pin senses the primary current though a sense resistor or a capacitive divider for lossless sensing. This input is not intended for a cycle-by-cycle control; hence the voltage signal must be filtered to get average current information. As the voltage exceeds a 0.8 V threshold (with 50 mV hysteresis), the soft-start capacitor connected to pin 1 is internally discharged: the frequency increases hence limiting the power throughput. Under output short circuit, this normally results in a nearly constant peak primary current. This condition is allowed for a maximum time set at pin 2. If the current keeps on building up despite this frequency increase, a second comparator referenced at 1.5 V latches the device off and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the Vcc pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.
7 LINE
Line sensing input. The pin is to be connected to the high-voltage input bus with a resistor divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage below 1.25 V shuts down (not latched) the IC, lowers its consumption and discharges the soft-start capacitor. IC’s operation is re-enabled (soft-started) as the voltage exceeds 1.25 V. The comparator is provided with current hysteresis: an internal 15 µA current generator is ON as long as the voltage applied at the pin is below 1.25 V and is OFF if this value is exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on the pin is top-limited by an internal zener. Activating the zener causes the IC to shut down (not latched). Bias the pin between 1.25 and 6 V if the function is not used.
8 DIS
Latched device shutdown. Internally the pin connects a comparator that, when the voltage on the pin exceeds 1.85 V, shuts the IC down and brings its consumption almost to a “before start-up” level. The information is latched and it is necessary to recycle the supply voltage of the IC to enable it to restart: the latch is removed as the voltage on the VCC pin goes below the UVLO threshold. Tie the pin to GND if the function is not used.
9 PFC_STOP
Open-drain ON/OFF control of PFC controller. This pin, normally open, is intended for stopping the PFC controller, for protection purpose or during burst-mode operation. It goes low when the IC is shut down by DIS > 1.85 V, ISEN > 1.5 V, LINE > 6 V and STBY < 1.25 V. The pin is pulled low also when the voltage on pin DELAY exceeds 2V and goes back open as the voltage falls below 0.3V. During UVLO, it is open. Leave the pin unconnected if not used.
10 GND
Chip ground. Current return for both the low-side gate-drive current and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return.

11 LVG
Low-side gate-drive output. The driver is capable of 0.3 A min. source and 0.8 A min. sink peak current to drive the lower MOSFET of the half-bridge leg. The pin is actively pulled to GND during UVLO.
12 VCC
Supply Voltage of both the signal part of the IC and the low-side gate driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of the IC.
13 N.C.

High-voltage spacer. The pin is not internally connected to isolate the high-voltage pin and ease compliance with safety regulations (creepage distance) on the PCB.

14 OUT

High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground.
15 HVG
High-side floating gate-drive output. The driver is capable of 0.3 A min. source and 0.8A min. sink peak current to drive the upper MOSFET of the half-bridge leg. A resistor internally connected to pin 14 (OUT) ensures that the pin is not floating during UVLO.
16 VBOOT
High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase with the low-side gate-drive. This patented structure replaces the normally used external diode.

SG6961

Description

The SG6961 is an 8-pin boundary mode PFC controller IC intended for controlling PFC pre-regulators. The SG6961 provides a controlled on-time to regulate the output DC voltage and achieve natural power factor correction. The maximum on-time of the external switch is programmable to ensure safe operation during AC brownouts. An innovative multi-vector error amplifier is built in to provide rapid transient response and precise output voltage clamping. A built-in circuit disables the controller if the output feedback loop is opened. The startup current is lower than 20JA and the operating current is under 4.5mA. The supply voltage can be up to 20V, maximizing application flexibility.

PIN CONFIGURATION

1 INV - lnverting Input of the Error Amplifier. INV is connected to the converter output via a resistive divider. This pin is also used for over-voltage clamping and open-loop feedback protection.

2 COMP -  The Output of the Error Amplifier. To create a precise clamping protection, a compensation network between this pin and GND is suggested.

3 MOT -  Maximum On Time. A resistor from MOT to GND is used to determine the maximum on-time of the external power MOSFET. The maximum output power of the converter is a function of the maximum on time.

4 CS -  Current Sense. lnput to the over-current protection comparator. When the sensed voltage across the sense resistor reaches the internal threshold (O.8V), the switch is turned off to activate cycle-by-cycle current limiting.

5 ZCD -  Zero Current Detection. This pin is connected to an auxiliary winding via a resistor to detect the zero crossing of the switch current. When the zero crossing is detected, a new switching cycle is started. If it is connected to GND, the device is disabled.

6 GND -  Ground. The power ground and signal ground. Placing a O.1pF decoupling capacitor between VCC and GND is recommended.

7 GD -  Driver Output. Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is 16.5V.

8 VCC - Power Supply. Driver and control circuit supply voltage.

POWER SUPPLY CIRCUIT 

32 INCH

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SAMSUNG BN44-00622B

VIPER12A

The VIPer12A combines a dedicated current mode PWM controller with a high voltage Power MOSFET on the same silicon chip. Typical applications cover off line power supplies for battery charger adapters, standby power supplies for TV or monitors, auxiliary supplies for motor control, etc. The internal control circuit offers the following benefits:
– Large input voltage range on the VDD pin accommodates changes in auxiliary supply voltage. This feature is well adapted to battery charger adapter configurations.
– Automatic burst mode in low load condition.
– Overvoltage protection in hiccup mode

PIN CONFIGURATION 

V DD - Power supply of the control circuits. Also provides a charging current during start up thanks to a high voltage current source connected to the drain. For this purpose, an hysteresis comparator monitors the VDD voltage and provides two thresholds:
- VDDon: Voltage value (typically 14.5V) at which the device starts switching and turns off the start up current source.
- VDDoff: Voltage value (typically 8V) at which the device stops switching and turns on the start up current source.

SOURCE -  Power MOSFET source and circuit ground reference.
DRAIN - Power MOSFET drain. Also used by the internal high voltage current source during start up phase for charging the external VDD capacitor.
FB - Feedback input. The useful voltage range extends from 0V to 1V, and defines the peak drain MOSFET current. The current limitation, which corresponds to the maximum drain current, is obtained for a FB pin shorted to the SOURCE pin.

STR- W6765

The STR-W6765 is a quasi-resonant topology IC designed for SMPS applications. It shows lower EMI noise characteristics than conventional PWM solutions, especially at greater than 2 MHz. It also provides a soft-switching mode to turn on the internal MOSFET at close to zero voltage (VDS bottom point) by use of the resonant characteristic of primary inductance and a resonant capacitor. The package is a fully molded TO-220, which contains the controller chip (MIC) and MOSFET, enabling output power up to 52 W with universal input or 110 W with a 230 VAC input. The bottom-skip mode skips the first bottom of VDS and turns on the MOSFET at the second bottom point, to minimize an increase of operating frequency at light output load, improving system-level efficiency over the entire load range. There are two standby modes available to reduce the input power under very light load conditions. The first is auto-burst mode operation that is internally triggered by periodic sensing, and the other is a manual standby mode, which is executed by clamping the secondary output. In general applications, the manual standby mode reduces the input power further compared to auto-burst mode. The soft-start mode minimizes surge voltage and reduces power stress to the MOSFET and to the secondary rectifying diodes during the start-up sequence. Various protections such as overvoltage, overload, overcurrent, maximum on-time protections and avalanche-energy-guaranteed MOSFET secure good systemlevel reliability.

PIN CONFIGURATION

1 D -  Drain MOSFET drain
2 NC -  Clipped No connection
3 S/GND - Source/ground terminal MOSFET source and ground
4 VCC  - Power supply terminal Input of power supply for control circuit
5 SS/OLP - Soft Start/Overload Protection terminal Input to set delay for Overload protection and Soft Start operation
6 FB - Feedback terminal Input for Constant Voltage Control and Burst (intermittent) Mode oscillation control signals
7 OCP/BD - Overcurrent Protection/Bottom Detection Input for overcurrent detection and bottom detection signals

ICE1PCS02

The ICE1PCS02/G is a 8-pin wide input range controller IC for active power factor correction converters. It is designed for converters in boost topology, and requires few external components. Its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the IC. The IC operates in the CCM with average current control, and in DCM only under light load condition. The switching frequency is trimmed and fixed internally at 65kHz. Both current and voltage loop compensations are done externally to allow full user control. There are various protection features incorporated to ensure safe system operation conditions. The internal reference is trimmed (5V+2%) to ensure precise protection and output control level. The ICE1PCS02/G is a design variant of ICE1PCS01 to incorporate the new input brown-out protection function and optimised to have a faster startup time with controlled peak startup current.

PIN CONFIGURATION

1 GND  - IC Ground
2 ICOMP -  Current Loop Compensation
3 ISENSE -  Current Sense Input
4 VINS - Brown-out Sense Input
5 VCOMP - Voltage Loop Compensation
6 VSENSE -  VOUT Sense (Feedback) Input
7 VCC  - IC Supply Voltage
8 GATE - Gate Drive Output

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SAMSUNG BN44-00330B

STR-W6053S PWM Regulator
The STR-W605xS series are power ICs for switching power supplies, incorporating a power MOSFET and a current mode PWM controller IC. Including a startup circuit and a standby function in the controller, the product achieves low power consumption, low standby power, and high cost-effectiveness power supply systems with few external components. The STR-W605xS internal MOSFET has a VDSSof 650 V (min), and an R DS(on) of 1.9 ohm (max) to 3.95 ohm (max) with a frequency of 67 kHz. Power output is rated at 45 to 90 W at 230 VAC input and 30 to 60 W at wide input range (85 to 265 VAC). The device is provided in an industry-standard TO-220 package, with heatsink mounting flange and pin 2 removed for increased supply isolation.

Applications:
For switching power supplies used in:
# White goods
# Consumer electronics
# Office automation
# Industrial equipment
# Communication equipment

PIN CONFIGURATION

1 D/ST MOSFET - drain, and input for startup current
2 – (Pin removed)
3 S/OCP MOSFET - source, and input for Overcurrent Protection detection signal
4 VCC -  Input for power supply for control circuit
5 GND - Ground
6 FB/OLP - Input for constant voltage control signal, and input for Overload Protection signal
7 BR - Input for Brown-In and Brown-Out Protection detection voltage.

UCC28061 PFC Controller

PIN CONFIGURATION

AGND - 6 - Analog ground: Connect analog signal bypass capacitors, compensation components, and analog signal returns to this pin. Connect the analog and power grounds at a single point to isolate high-current noise signals of the power components from interference with the low-current analog circuits.
COMP - 5 - Error amplifier output: The error amplifier is a transconductance amplifier, so this output is a high-impedance current source. Connect voltage regulation loop compensation components from this pin to AGND. The on-time seen at the gate drive outputs is proportional to the voltage at this pin minus an offset of approximately 125 mV. During soft-start events (undervoltage, brownout, disable or output over voltage), COMP is pulled low. Normal operation only resumes after the soft-start event clears and COMP has been discharged below 0.5 V, making sure that the circuit restarts with a low COMP voltage and a short on-time. Do not connect COMP to a low-impedance source that would interfere with COMP falling below 0.5 V.
CS - 10 -  Current sense input: Connect the current sense resistor and the negative terminal of the diode bridge to this pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. As input current increases, the voltage on CS goes more negative. This cycle-by-cycle over-current protection limits input current by turning off both gate driver (GDx) outputs when CS is more negative than the CS rising threshold (approximately –200 mV). The GD outputs remain low until CS falls to the CS falling threshold (approximately –15 mV). Current sense is blanked for approximately 100 ns following the falling edge of either GD output. This blanking filters noise that occurs when current switches from a power FET to a boost diode. In most cases, no additional current sense filtering is required. If filtering is required, the filter series resistance must be under 100Ω to maintain accuracy. To prevent excessive negative voltage on the CS pin during inrush conditions, connect the current sensing resistor to the CS pin through a low value external resistor. GDA 14 O Channel A and channel B gate drive output: Connect these pins to the gate of the power FET for each phase through the shortest connection practical. If it is necessary to use a trace longer than 0.5 GDB 11 O inch (12.6 mm) for this connection, some ringing may occur due to trace series inductance. This ringing can be reduced by adding a 5-Ω to 10-Ω resistor in series with GDA and GDB.
HVSEN - 8 -High voltage output sense: The UCC28061 incorporates FailSafe OVP so that any single failure does not allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE and HVSEN and shuts down the PWM if either pin exceeds the appropriate over-voltage threshold. Using two pins to monitor for over-voltage provides redundant protection and fault tolerance. HVSEN can also be used to enable a downstream power converter when the voltage on HVSEN is within the operating region. Select the HVSEN divider ratio for the desired over-voltage and power-good thresholds. Select the HVSEN divider impedance for the desired power-good hysteresis. During operation, HVSEN must never fall below 0.8 V. Dropping HVSEN below 0.8 V puts the UCC28061 into a special test mode, used only for factory testing. A bypass capacitor from HVSEN to AGND is recommended to filter noise and prevent false over-voltage shutdown.
PGND - 13 -Power ground for the integrated circuit: Connect this pin to AGND through a separate short trace to isolate gate driver noise from analog signals.
PHB - 4 - Phase B enable: This pin turns on/off channel B of the boost converter. The commanded on-time for channel A is immediately doubled when channel B is disabled, which helps to keep COMP voltage constant during the phase management transient. The PHB pin allows the user to add external phase management circuitry if they desire. To disable phase management, connect the PHB pin to the VREF pin.

PWMCNTL -  9 -  WM enable logic output: This open-drain output goes low when HVSEN is within the HVSEN good region and the ZCDA and ZCDB inputs are switching correctly if operating in two-phase mode (see PHB Pin). Otherwise, PWMCNTL is high impedance.
TSET  - 3 - Timing set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the on-time versus COMP voltage and the minimum period at the gate drive outputs.
VCC - 12-  Bias supply input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect a 0.1-µF ceramic bypass capacitor from this pin to PGND with the shortest possible board trace. This supply powers all circuits in the device and must be capable of delivering 6 mA dc plus the transient power MOSFET gate charging current.
VINAC - 7 - Input ac voltage sense: For normal operation, connect this pin to a voltage divider across the rectified input power mains. When the voltage on VINAC remains below the brownout threshold for more than the brownout filter time, the device enters a brownout mode and both output drives are disabled. Select the input voltage divider ratio for the desired brownout threshold. Select the divider impedance for the desired brownout hysteresis.
VREF - 15 - Voltage reference output: Connect a 0.1-µF ceramic bypass capacitor from this pin to AGND. VREF turns off during VCC undervoltage and VSENSE disable to save supply current and increase efficiency. This 6 VDC reference can be used to bias other circuits requiring less than 2 mA of total supply current.
VSENSE - 2 -Output dc voltage sense: Connect this pin to a voltage divider across the output of the power converter. The error amplifier reference voltage is 6 V. Select the output voltage divider ratio for the desired output voltage. Connect the ground side of this divider to ground through a separate short trace for best output regulation accuracy and noise immunity. VSENSE can be pulled low by an open-drain logic output or 6-V logic output in series with a low-leakage diode to disable the outputs and reduce VCC current. If VSENSE is disconnected, open-loop protection provides an internal current source to pull VSENSE low, turning off the gate drivers.
ZCDB - 1 - Zero current detection inputs: These inputs expect to see a negative edge when the inductor current in the respective phases go to zero. The inputs are clamped at 0 V and 3 V. Signals should be coupled ZCDA 16 I through a series resistor that limits the clamping current to less than ±3 mA. Connect these pins through a current limiting resistor to the zero crossing detection windings of the appropriate boost inductor. The inductor winding must be connected so that this voltage drops when inductor current decays to zero. When the inductor current drops to zero, the ZCD input must drop below the falling threshold, approximately 1 V, to cause the gate drive output to rise. When the power MOSFET turns off, the ZCD input must rise above the rising threshold, approximately 1.7 V, to arm the logic for another falling ZCD edge.

POWER SUPPLY AND BACK LIGHT INVERTER CIRCUIT DIAGRAM 

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